Modern electronic circuits are often designed and subsequently manufactured using software tools, commonly referred to as electronic design automation (EDA) tools. Typically, a circuit designer will utilize a software design tool or hardware description language to describe the intended functionality of the circuit. The high-level functional description is provided to a synthesis tool that converts the intended functionality to a netlist, which represents the instances of logic gates and/or other hardware components and their corresponding interconnections that, when configured, will provide the intended functionality. A software placement tool places instances of the logic gates and/or hardware components of the netlist in an optimal manner. Often, the placement tool obtains and places instances of the logic gates and/or hardware components using a standard cell library, which includes a number possible logic gates and/or hardware components that may be used to implement the netlist in the particular technology configured as cells that are standardized to have a fixed dimension. After placement, a software routing tool (or router) optimally creates interconnections between the placed cells based on the netlist taking into account design rules for the particular technology, resulting in a completed layout for the circuit. A completed layout for a circuit or device may be encoded in a suitable file format, such as Graphical Database System II (or GDSII) format, on a computer-readable medium that may be subsequently provided to a foundry or mask shop to translate the completed layout into photomasks that may then be used to fabricate the circuit.
Often, standard cells of the standard cell library are designed to provide, for each input/output pin (or terminal) of the cell, a sufficient number of possible locations (or a sufficiently large area) that may be used to form connections to the pins and facilitate routing to/from placed instances of the cell by the routing tool without violating design rules. However, the ability of the routing tool to route to/from each placed cell will vary depending on the placement of that cell within the layout, its neighboring cells, and the design rules for the technology, along with other factors. Thus, it is difficult or otherwise impractical to exhaustively test the ability of the routing tool to route to/from and/or connect to each pin of each standard cell in the standard cell library. As a result, it is difficult to identify issues pertaining to routability and/or connectivity until the standard cell library is being utilized by the placement tool and/or routing tool outside of the testing environment to design new circuits, at which point, it can be difficult to debug and identify what the routability and/or connectivity issue is attributable to.